For example, a high voltage IC for inverter driving, etc. is disclosed in U.S. Pat. No. 5,736,774 and Proceeding of ISPSD 2004, page 385.
FIG. 7 shows a typical sectional view of a high voltage IC 9 of the background art using a SOI substrate and trench separation.
In the high voltage IC 9 shown in FIG. 7, a low electric potential (GND) reference circuit, a high electric potential (floating) reference circuit and a level shift circuit are respectively arranged in a SOI layer 1a of the SOI substrate 1 having a burying oxide film 3. In the low electric potential (GND) reference circuit, a GND electric potential is set to a reference electric potential, and this low electric potential reference circuit is operated at ±15V. For example, the high electric potential (floating) reference circuit is operated with a high electric potential of 600V or more as a reference electric potential in a high voltage IC used in inverter driving for vehicle mounting. The level shift circuit transmits signals between the low electric potential reference circuit and the high electric potential reference circuit.
As shown in FIG. 7, each of forming areas of the GND reference circuit, the floating reference circuit and the level shift circuit is insulated (dielectric) and separated by the burying oxide film 3 of the SOI substrate 1 and a side wall oxide film 4s of a trench 4. In the high voltage IC 9, the rear face of a support substrate 2 is connected to GND to stabilize the electric potential.
In the level shift circuit of the high voltage IC 9, a circuit element of a high withstand voltage is required to connect the low electric potential reference circuit and the high electric potential reference circuit. For example, in the high voltage IC 9 of 600V or more, a circuit element having a withstand voltage of 600V or more is required. A lateral double-diffused MOS transistor (LDMOS) 9a of the forming area of the level shift circuit shown in FIG. 7 takes a so-called SOI-RESURF structure (double RESURF structure) in which a depletion layer is spread from both a PN junction face located in the surface layer portion of the SOI layer 1a and the burying oxide film 3 to secure the withstand voltage.
As shown in FIG. 7, the high voltage in the level shift circuit is applied to a drain D of LDMOS 9a. In LDMOS 9a of FIG. 7, the withstand voltage of the lateral direction of a section is secured by the SOI-RESURF structure formed by a surface p-type impurity layer and the burying oxide film 3. Further, with respect to the withstand voltage of the longitudinal direction of the section, the high voltage applied between the drain D and the ground (GND) is partially divided by the SOI layer 1a of low concentration and the burying oxide film 3, and an electric field in the SOI layer 1a is relaxed.
FIGS. 8A and 8B show simulation results of an electric potential distribution at a high voltage applying time with respect to a semiconductor device 9b in which LDMOS similar to the above LDMOS 9a is formed. FIG. 8A is a typical sectional view of the semiconductor device 9b. FIG. 8B is a view showing the electric potential distribution at a breakdown time. In the semiconductor device 9b of FIGS. 8A and 8B, portions similar to those of LDMOS 9a of FIG. 7 are designated by the same reference numerals.
As shown in FIG. 8B, the withstand voltage of the semiconductor device 9b shown in FIG. 8A is 640V. In FIG. 8B, an equipotential line is close in the longitudinal direction on the drain D side of LDMOS formed in the SOI layer 1a. In other words, in the semiconductor device 9b of FIG. 8A, an electric force line is concentrated on the drain D side of LDMOS at the high voltage applying time. Therefore, the withstand voltage 640V of the semiconductor device 9b is applied in the longitudinal direction of the section of the SOI layer 1a on the drain D side of LDMOS.
The withstand voltage V of the longitudinal direction of LDMOS formed in the SOI layer 1a is generally generated by connecting the rear face of the support substrate 2 to GND, and is represented by the following formula No. 1.V∝(ts/2+3tox)×ts/ε0  (F1)
In the formula No. 1, ts is the thickness of the SOI layer 1a, and tox is the thickness of the burying oxide film 3, and ε0 is the dielectric constant of the burying oxide film 3. Accordingly, as can be seen from the formula No. 1, the withstand voltage of the longitudinal direction is determined by the thickness ts of the SOI layer 1a, the thickness tox of the burying oxide film 3 and the dielectric constant ε0 of the burying oxide film 3. Accordingly, it is necessary to thicken the thickness ts of the SOI layer 1a, or thicken the thickness tox of the burying oxide film 3 so as to improve the withstand voltage of the semiconductor device 9b by a size design. For example, when a high withstand voltage of 1000V or more is intended to be obtained, the burying oxide film thicker than 5 μm and the SOI layer thicker than 50 μm are required. However, the thickness ts of the SOI layer 1a has a limit thickness of 20 μm shown in FIG. 8A from a limit of a processing technique of the trench 4 formed in a subsequent process. Further, the thickness tox of the burying oxide film 3 has a limit film thickness of 4 μm from the limits of a warp amount of a wafer of the SOI substrate 1 formed by sticking and cost of a raw ore. Therefore, in the semiconductor device 9b shown in FIGS. 8A and 8B, it is difficult to secure a withstand voltage greater than 640V. Accordingly, in LDMOS 9a having a structure similar to that of the semiconductor device 9b of FIGS. 8A and 8B and applied to the level shift circuit of the high voltage IC 9 of FIG. 7, it is impossible to secure a withstand voltage of 1200V required in an EV vehicle, etc.